===============================================================================

 Ptune3 is SH7305 CPG&BSC&DBSC tuning utility for PRIZM fx-CG50/Graph 90+E  v0.25

 copyright(c)2014/2015/2016/2017/2018/2019/2020/2023 by sentaro21
 e-mail sentaro21@pm.matrix.jp

===============================================================================

ẼJ[OtdACASIOfx-CG10/20̌p@ƂȂfx-CG50/Graph 90+E 2017Nt蔭Jn܂B
fx-10/20ƓSH4A̗pĂAPtune2l̃`[AbvEc[ƂPtune3JłB

fx-CG50/Graph 90+ERAMSDRAMɕύXꂽȊO͑傫ȕύX_͖͗lłB

E
@200MHzȏ܂ŃI[o[NbNł܂B
@̓EgIɑ肵܂Biꕔj
@g/EGCgݒt@NVL[ɕۑł܂B
@ݒZ[uĂΎNɎIɓǂݍ܂܂B

E_
@xAbvɉďd܂B
ifx-CG50/Graph 90+E͏d͂팸ĂANbNłfx-CG10/206x̏d͂łBj
@\ɃeXgĂȂ̂Ŗm̕sNĂsvcł͂܂B

========================== !!! ============================================
̃c[͈Sɓ삷悤ɏ\ӂč쐬Ă܂A
Ȃ̓dɏdȃ_[W^鋰ꂪ܂B
قƂǂ̏ꍇ̓ZbgŕAł܂Ad̃VXetbVROMɂ䂦ɁA
BIOS܂OS̈ւ̌돑Nꍇɂ͊mɍċNs\Ɋׂ܂B
c[̎gp̓obNAbvƂłȂ̐ӔCɂĂ肢܂B
҂͂̃c[̎gp̌ʂɂĂȂӔCȂ̂ƂĂ܂B
===============================================================================

-------------------------------------------------------------------------------
CPU
-------------------------------------------------------------------------------
SH7305          lTXSH7724iSH7730jɔɂ悭CPUłA
                dpɃJX^}CYꂽCPUłB
                LbV̓CXgNVAf[^Ƃ32KBA
                2{̃pCvX[p[XJCPUłB
                ו̏ڂA\̓lTXPDF(SH7724,SH7730)QƂĂB
                ł͈ĂiƎvj܂B

-------------------------------------------------------------------------------
CPG(NbNpXWFl[^)                     Qƌ: SH7724 f[^V[g
-------------------------------------------------------------------------------

FLL             FLLH̒{B
                FLLH32.768KHz{Ċ{NbN𐶐܂B
                FLL̒{̓ftHg900łB
                SH7305̊{NbN32.768KHz900{1/2ɂ14.7456MHz
                FLLHo͂܂B
                SH7724̃}jAł20MHz`33MHz܂łƂ܂A
                20MHzȉA33MHzȏł\Ȃ悤łB

PLL             PLLH̒{B
                FLLHo͂{NbN{ĊeNbŇɂȂNbN𐶐܂B
                ftHg16{ɐݒ肳Ă܂B
                14.7456MHz * 16 = 235.9296MHz
                1{`32{܂Őݒł܂B
		fx-CG10/20Ƃ͈33{1{ɖ߂Ă܂̂32{܂łɐĂ܂B

IFC             CPUNbN̕B
                PLLŐꂽNbN𕪎CPURAɋNbN𐶐܂B
                fx-CG50ł̓ftHg1/2ɐݒ肳Ă117.96MHzœ삵Ă܂B
                ő280MHzx܂œ\Ȃ悤łB

SFC             SNbN̕B
                PLLŐꂽNbN𕪎SuperHywayoXɋNbN𐶐܂B
                ftHg1/4ɐݒ肳Ă58.98MHzœ삵Ă܂B
		ő200MHzx܂œ\Ȃ悤ł160MHzx܂łɂSłB

BFC             oXNbN̕B
                PLLŐꂽNbN𕪎ăoXɋNbN𐶐܂B
                ftHgł1/4ɐݒ肳Ă58.98MHzœ삵Ă܂B
                o[WPtune3ɂĂSDRAM̓Ei100+MHzxjgEƂȂ܂B

PFC             ӃNbN̕B
                PLLŐꂽNbN𕪎I/OɋNbN𐶐܂BiRS232Cj
                ftHgł1/8ɐݒ肳Ă29.49MHzœ삵Ă܂B
		CG10/20}[WmۂĂ̂荂gł삵܂B
                ő50MHzx܂ł͓mFłĂ܂B

                IFC,SFC,BFC,PFC̕SH7724SH7730Ƃ͈1/2̔{݂̂łB
                0000: 1/2
                0001: 1/4       IFC ftHg
                0010: 1/8       SFC,BFC ftHg
                0011: 1/16      PFC ftHg
                0100: 1/32
                0101: 1/64

                e
                IFC >= SFC >= BFC >= PFC
                ̊֌WۂȂƗ\ʓN܂B
                ꂼ̔䗦Ă\ʓ삪N\܂B
                ̃c[ł͐퓮삷͈͓Ɏ܂B


-------------------------------------------------------------------------------
BSC(oXXe[gRg[)                       Qƌ: SH7724/SH7730 f[^V[g
-------------------------------------------------------------------------------
oXXe[gRg[͊eEGCg̐ݒs܂B
WX^̍\SH7724ƓƎv܂B

CS0BCR, CS0WCR  : FLASH ROM GA
iCS2BCR, CS2WCR  :i main  RAM GAj
CS3BCR, CS3WCR  : SDRAM GA
CS5ABCR,CS5AWCR : LCDC
̑̃WX^Ɏg͕słB

ROM             ANZX^C100nsNOR^tbVROMi32MB)̗pĂ
                OSAhC̊i[ꏊƂĎgpĂ܂B
                ʏgpł͏݂͂܂NȂłA
                dItŎIɃtbVROMɃC̓eobNAbv̂
                dItŖtbV݂̏܂B
                EGCgl̐ݒ肪ႷƓǂݍ݂⏑݃R}hɃG[A
                BIOSOSGAɊԈď݂ƊmɃtbV̓e
                j󂳂Ă܂܂B
                ̃c[ł͂ȂȂ悤ȃEGCglɎݒ肵܂A
                EGCglɗ]TȂꍇɂ͌듮삷\܂B

RAM             ANZX^C7nsSDRAMi8MBj̗pĂA
                CAhC̃[NGAƂĎgp܂B
		CL2ɂ100MHzACL3ɂ143MHz܂łiłAł100MHzȏɂ͏グ邱ƂoĂ܂B


EGCg        tbVROM,RAM̃ANZXɑ}EGCglB
                ROM̃ftHgEGCgl        8@(fx-CG50)
                RAM̃ftHgEGCgl        CL2

                ̃EGCg⃁ԃANZX̃ACh^CAl߂Ƃ
                P邾Ŏsx3`5ɂȂ܂B


========================== !!! ============================================
̃c[͈Sɓ삷悤ɏ\ӂč쐬Ă܂A
Ȃ̓dɏdȃ_[W^鋰ꂪ܂B
قƂǂ̏ꍇ̓ZbgŕAł܂Ad̃VXetbVROMɂ䂦ɁA
BIOS܂OS̈ւ̌돑Nꍇɂ͊mɍċNs\Ɋׂ܂B
c[̎gp̓obNAbvƂłȂ̐ӔCɂĂ肢܂B
҂͂̃c[̎gp̌ʂɂĂȂӔCȂ̂Ƃ܂B
===============================================================================

-------------------------------------------------------------------------------
C
-------------------------------------------------------------------------------
----------------------------------
 FLL:x900          * 14.75MHz
 PLL:x16           *235.93MHz
 IFC:1/2  CPU      *117.96MHz
 SFC:1/4  roR 8    * 58.98MHz
 BFC:1/4  CL  2    * 58.98MHz
 PFC:1/8           * 29.49MHz
messeage area / benchmark score
[function key]
-----------------------------------

roR: ROM[hANZXEGCgTCN@:댯͈ @ :EGCg点\B
CL : SDRAM CLl


-------------------------------------------------------------------------------
gp@
-------------------------------------------------------------------------------

-[UP]           ǂ邩I܂B (FLL,PLL,SFC,BFC,PFC)
-[DOWN]

-[LEFT]         iKグ܂B
-[RIGHT]        iK܂B

-[SHIFT]+[UP]   FLL̕ύX\ɂȂ܂B(ZbgAbvɂ+[SHIFT]ɕύXł܂B)

-[F1]   d샊Zbg̃ftHgɖ߂܂B                  CPU 118MHz, PLLx16, bus  58MHz  ftHg
-[F2]   F2L[ɋLݒĂяo܂B  ݒ=>      CPU  59MHz, PLLx32, bus  29MHz, EGCg팸
-[F3]   F2L[ɋLݒĂяo܂B  ݒ=>      CPU 118MHz, PLLx32, bus  58MHz, EGCg팸
-[F4]   F2L[ɋLݒĂяo܂B  ݒ=>      CPU 236MHz, PLLx32, bus  58MHz, EGCg팸
-[F5]   F2L[ɋLݒĂяo܂B  ݒ=>      CPU 192MHz, PLLx26, bus  95MHz, EGCg팸
-[F6]   ȒPȃx`}[Ns܂B
        CPŨXRAfx-9860Gadd-in "UTIL"Ɠl̃^C}[ݒɂ郋[v񐔂JEg܂B
        ̃c[ł100msԂł̃[v񐔂1/100ɂlłB
        50msԂ̃ANZX(ROM,RAM,I/O)̉񐔂JEg܂B
        ؂ւPutDsipDDPbԂɉĂяo邩̉񐔂v܂B(fps)

-[SHIFT]
    -[F1]       CɃZ[u܂BNɎIɓǂݍ܂܂B
    -[F2]       ݂̐ݒF2L[ɋL܂B
    -[F3]       ݂̐ݒF3L[ɋL܂B
    -[F4]       ݂̐ݒF4L[ɋL܂B
    -[F5]       ݂̐ݒF5L[ɋL܂B
    -[F6]       C胍[h܂B

-[OPTN]         eEGCgɂEgꗗ\܂B
    -[F4]       ݒ܂B
    -[F5]       ROM/RAM̌EgRAM[h/CgEgꗗ\܂B
                RAM̃CgEg͂Ƃ납LтȂȂ蓪łɂȂ܂SNbNoXNbŇEƂȂ܂B
    -[F6]       eEGCgɂő哮gIɌv܂B

-[VARS]
    -[F1]       register display  FRQCR
    -[F2]       register display  BCR/WCR тɐ؂ւ܂B
    -[F3]       iROM)CS0BCR iRAM)CS2BCR̃EGCgݒ܂B
                J[\L[őI
        -[F1]   +
        -[F2]   -
        -[F4]   EGCgl̏܂B

    -[F4]       iROM)CS0WCR iRAM)CS2WCR̃EGCgݒ܂B
                J[\L[őI
        -[F1]   +
        -[F2]   -
        -[F4]   EGCgl܂B
    -[F5]       CS5ABCR CS5BBCR̃EGCgݒ܂B
                J[\L[őI
        -[F1]   +
        -[F2]   -
        -[F4]   EGCgl̏܂B

    -[F6]       CS5AWCR CS5BWCR̃EGCgݒ܂B
                J[\L[őI
        -[F1]   +
        -[F2]   -
        -[F4]   EGCgl܂B

-[PRGM]
    -[F1]       CS3BCR CS4BCRWX^ݒ܂B
    -[F2]       CS3WCR CS4WCRWX^ݒ܂B
    -[F3]       CS5ABCR CS5BBCRWX^ݒ܂B
    -[F4]       CS5AWCR CS4BWCRWX^ݒ܂B
    -[F5]       CS6ABCR CS6BBCRWX^ݒ܂B
    -[F6]       CS6AWCR CS6BWCRWX^ݒ܂B

-[EXIT]         exit

-[AC]           ʂ܂B

-[EXE]          x`}[NIĂꍇɍēxs܂B

-[*]            ROM̃EGCgl𑝂₵܂B
-[/]            ROM̃EGCgl炵܂B
                ɉꍇ́A`FbNn܂܂B
                G[oꍇ̓EGCgl͌点܂B

-[X^2]
-[^]            XyNggU@\On/Off؂ւ܂B

-[SETUP]                                     ݒ
        ROMv̓}[Wݒ 0-15%       @5%    ( 1%ȉ̐ݒ͊댯łB)@EGCggꗗ̓Zbg܂B
        RAMv̓}[Wݒ 0-15%       @5%    ( 1%ȉ̐ݒ͊댯łB)@EGCggꗗ̓Zbg܂B
        PLLgőlݒ                     800MHz
        CPUgőlݒ                     275MHz
        Shwgőlݒ                     150MHz
        Busgőlݒ                     100MHz
        I/Ogőlݒ                      50MHz
        X^[gAbṽ`FbN        off
        F1L[ꍇyes/no `FbN     off
        EGCgIɉ                on
        RAM@WWIɏグ           off
        ROM IWWIɉ                 on
        PFCIɏグ                     on
	VtgFLL\                 off
        drd\                            on
	g\                          on


-------------------------------------------------------------------------------
ő僁g̎v
-------------------------------------------------------------------------------
̃c[ɂĂ̓̓Ev邱ƂdvłB
ROM̌vɂ͂܂ŏɂǂ̃GAiŜ̒64KBjԒxv܂B
̈ԒxGAŊeEGCglɂEgv܂B
vƂĂPȂ̂ŁAAhXAēxǂ݂ĈႢȂOkA
ႢNGƂƂɂĂ܂B

SDRAMeXg̓EGCgύXẴeXgoȂ̂ŁA
VXěƂĂ̌EeXgƂȂ܂B
VXeG[oꍇ̂ł̂Ƃ̓ZbgK{łB
G[oȂĂSDRAM̃eXgsȂ̓Zbg邱Ƃ𐄏܂B

v0.10SDRAMeXg݂͌̃EGCgݒł̃eXgɂȂĂ܂B
^C~Ol߂ƓEĂ܂AeXgɃG[ɂȂVXeG[Nꍇ܂B
̏ꍇ́AZbgΕA܂B

-------------------------------------------------------------------------------

-------------------------------------------------------------------------------
gEeXgуeXgAeeXgɂUSBڑԂł͎sȂŉB

RS232CI/ONbNɈˑ܂BʐMꍇI/ONbN𓯂ɂĂB


-------------------------------------------------------------------------------
g̃YΉ						ver.0.20ȍ~
-------------------------------------------------------------------------------
CG10/20ł͓PLLvZgƎۂ̓gvĂ܂A
CG50/Graph90+Eł͎Ɩ1.6قǒႢgœ삵Ă悤łB
ver.0.20ۂ̓g\ɑΉ܂B
mȕ␳l͕Ȃ̂ŁAbIɓPLLg900/914悶g\܂B
ZbgAbvœPLLg\Ƃ̐ؑւ\łB

(QlN)
http://www.casiopeia.net/forum/viewtopic.php?f=25&t=7327

(ver.0.21)
CG50ł̓NbNŨXyNggU@\ftHgŃCl[uĂA
ۂ̓gPLLvZgႭȂĂ邱ƂmFł܂B
0.21ȍ~ł̓XyNggU@\Cl[uĂꍇ͉ʕ\̕\Lς܂B


-------------------------------------------------------------------------------
ӎ
-------------------------------------------------------------------------------
̃c[PoveriAshbad쐬j\[XɊgāA
PrizmSDK 0.3iPtune2)
ɂč쐬ꂽPtune2Co[WłB

fxReverse project documentation,
SuperH-based fx calculators,
Cemetech WikiPrizm,
y[U[̊Fl̊e͌ʂɊӂ܂B

CG50ȑOPtune3 ver0.01~0.04쐬ł̂TI-PlanetCritorɃeXgĂłB
ǂ肪Ƃ܂B


̃c[Fl̂ɗĂ΍KłB

-------------------------------------------------------------------------------
CZX
-------------------------------------------------------------------------------
̃\tgEGA̓t[\tgEGAłB
CZXGPLv2ɏ܂B

-------------------------------------------------------------------------------
v0.25   2023.10.24	[F5]̐ݒPLLx25ɕύX܂B

v0.24	2020.2.20	"X"ZL"x"ɕύX܂B

v0.23	2020.1.3	Colonl񋟂̃ACRf[^ɂt@NVL[̕\P܂B

v0.22	2019.8.29	d\l9C܂B

v0.21	2019.2.20	XyNggU@\On/Off@\ǉ܂B
			[X^2][^]L[On/Off؂ւ܂B

v0.20	2018.8.19	ROM/SDRAMeXgvOC܂B
     	2018.8.18	ۂ̎gƂ̃Ylĕ\悤ɂ܂BiZbgAbvŐݒł܂Bj
			(b␳l@PLLZog * 900 / 914)

v0.10   2017.10.1@@	RAMeXgvOݒ肳ꂽԂōs悤ɏC܂B
			SDRAM̃^C~Ol߂RAMeXgɃG[ɂȂVXeG[Nꍇ܂B
			̏ꍇ́AZbgΕA܂B


v0.05   2017.7.20@@	RAMeXgvOC܂B
		@@@@ۑȂWX^̂C܂B(CS3BCR,CS3WCR)
			ÑftHgݒύX܂B


v0.04   2017.4.19      	ROMeXgvOC܂B
                       	CS2WCR ̃WX^\SH7724ɖ߂܂. ( SH7730 -> SH7724 )
                       	PLL搔̍ől32ɐ܂B


v0.03   2017.4.18      	ROMeXg̃oOC܂B

v0.02   2017.4.17      	CS2WCR,CS3WCR register\SH7730ɕύX܂. ( SH7724 -> SH7730 )
                       	SDRAM̓^C~Oݒ肪\ɂȂ܂B
                       	PLL搔̍ől33ɐ܂B

v0.01   2017.4.15      	


